1. Field of the Invention
The invention relates to a digital counter, and particularly to a digital counter having a carry chain isolated from a timing critical path.
2. Discussion of the Related Art
When the field of digital microprocessor electronics was in its infancy, gate speeds and electronic group velocities in conducting interconnectors (.about.10.sup.10 cm/s) were so relatively fast compared to processor speeds that the time for a signal to travel from one end of a bus to the other, and switch any gates along the way, was negligible. Today, 333 Megahertz (three nanosecond (ns)) processors are being marketed at retail computer stores. One Gigahertz (one nanosecond) processors are around the corner. Since an electron travelling at 10.sup.10 cm/s only travels 10 cm in one nanosecond, and gate technology has advanced only into the nanosecond regime, limited electron velocities and gate switching speeds are now necessitating more efficient digital electronics components designs, including those for counters as addressed in this application.
FIG. 1 shows a one-bit counter of the prior art. The counter has a modulus of two since it can be in either of two data states. The counter of FIG. 1 includes a D flip-flop 2 connected to a +1 adder 4. Each of the flip-flop 2 and the +1 adder 4 is a network of logic gates. The flip-flop 2 is a clock synchronized D latch that is enabled at periodic clock edges. The +1 adder 4 performs combinatorial logic and is incrementable by one.
FIG. 2 shows the counter of FIG. 1 with a multiplexer 6 connected conventionally between the flip-flop 2 and the +1 adder 4. The output of the multiplexer 6 is received by the input of the flip-flop 2. The multiplexer 6 multiplexes the outputs of both the +1 adder 4 and the flip-flop 2. The output of the multiplexer 6 is shown to be controlled by a counter enable (CE) signal. The flip-flop 2 is synchronized by an internal clock.
The outputs of more than one flip-flop 2 may each be received by an input bus of the +1 adder 4 to form a conventional multiple bit counter 8, as shown in FIG. 3. Generally, an n-bit counter can be said to have a modulus of 2.sup.n because it can represent, in binary, a number between zero and (2.sup.n -1). The multiple bit counter 8 of FIG. 3 includes multiple combinations of multiplexers 6 and flip-flops 2. Each multiplexer 6 is shown receiving a CE signal 10. The CE signal 10 is coming in from an external source and synchronizing and controlling the output of each multiplexer 6.
FIG. 4 shows a conventional 6-bit counter comprising six flip-flops 2, one for each bit. Advances in digital electronics have enabled higher modulus counters including today's 64 bit PCI controller. As shown in FIG. 4, a clock signal CLK is received by each flip-flop 2. The clock signal CLK carries a sufficient potential to enable each flip-flop 2 along the width of the bus and switches each latch 2 in one clock period or less.
A 64-bit PCI controller under existing standard allows only a three ns setup time to latch the CE signal 10. An outbound FIFO read pointer, or counter, has to decide whether to advance to the next count based on the state of the IRDY# or TRDY# flip-flop CE signals. If the read pointer has to advance to the next count, it has to change state at the rising edge of the PCI clock. The same clock is also used to latch the IRDY# and TRDY# control signals.
A first problem arises that, when CE signals change data states, they must convey information to all of the multiplexers 6 of the conventional counter before switching again. It is, however, difficult to feed multiple multiplexer inputs and latch the gates along a high modulus counter bus with only a one-to-three nanosecond CE signal period within which to do so.
A second problem arises that the CE signal 10 voltage of conventional counters must be great enough to enable a load to be dropped on each multiplexer 6-flip-flop 2 combination along a bus. The more multiplexers 6 there are, corresponding to an increased modulus of the counter, the more propagation delay is incurred on the CE signal line to switch each latch and generate a pulse for output to, e.g., an adder. The voltage is fixed at 3.3 volts.
In summary, a problem exists with current counter designs. On the one hand, having a faster digital system means less time is available for a counter CE signal 10 to supply its information to each critical point, i.e., latch, along the bus of the counter. On the other hand, having higher modulus counters means that more time is needed for the CE signal 10 to accomplish this task using conventional design techniques.